Microarchitecture Support for Interconnect Power- aware Instruction Permutation

This paper proposes a new instruction permutation encoding mechanism to deal with power dissipation issue on interconnect bus between processor and memory. When program executable code is loaded into memory, instructions are re-scheduled, block by block, into a power efficient format. As a result, on cache miss when instruction block from memory is required, power consumption during transmission of instruction between memory and processor end on interconnect bus is reduced. Reorder operation does not require any encoding/decoding circuitry. In order to restore instructions into its original order, an index table is employed with a reasonable area, power and access time overhead. Results based on the SPEC CPU2000 benchmark suit show that selfand coupling capacitance switching is reduced by 40% and 30%, respectively, with an area overhead of 14% at 65 nm technology node. It is also shown that intra-group instruction permutation after opcode permutation does not reduce selfand coupling switching activities by a significant amount.